1. Field of the Invention
The present invention relates to a semiconductor memory device having a test mode setting circuit. More specifically, the present invention relates to a semiconductor memory device having a test mode setting circuit for setting a dynamic RAM (hereinafter referred to as DRAM), comprising a plurality of memory cells each consisting of an insulated gate type field effect transistor (hereinafter referred to as MOS transistor) and a capacitance, at a mode for supply voltage fluctuation test (hereinafter referred to as V bump test).
2. Description of the Prior Art
Due to the development of the technology of manufacturing semiconductor integrated circuits and to a strong desire to reduce cost, the degree of integration of a DRAM has increased quadruple in about three years. DRAMs of 4M bit capacitance have come into use. When data "0" are written in all of the memory cells, the data "0 " are read from all memory cells, data "1 " are written in all memory cells and the data "1 " are read from all memory cells in this DRAM in the cycle time of 10 .mu.sec (maximum pulse width of a RAS (row address strobe) signal), the time T1 for testing is represented by the following equation (1). ##EQU1## In a common dynamic RAM, the aforementioned test should be carried out under four different conditions, namely, at the maximum value 5.5 V and minimum value 4.5 V of the operational range of supply voltage, and at higher temperature 70.degree. C. and lower temperature 0.degree. C. of the operational temperature range.
In this case, the time T2 for testing will be EQU T2=160 sec.times.4=640 sec (2)
the above value is very long as a time for testing an integrated circuit, and this lowers the production yield and increases cost.
In addition, sometimes the above described test is not sufficient for detecting defects. Other tests should be carried out with different combinations of timings of input signals, order of designating addresses, patterns of data to be written in the memory cells, and so on. Such tests require a long period of time.
A supply voltage fluctuation test (hereinafter referred to as V bump test) has been employed, which is capable of testing operation margins of these memory cells in a short period of time, in consideration of the fact that almost all memory cells malfunction in the combination test have small operation margins. However, as the memory capacitance becomes larger and larger, the effect of V bump test becomes smaller. The reason for this will be described in the following with reference to FIGS. 1 to 5.
FIG. 1 is a block diagram showing a schematic structure of a conventional DRAM to which the present invention is applied.
Referring to FIG. 1, the DRAM comprises a memory cell array MA, and address buffer AB, an X decoder ADX, an Y decoder ADY, a sense amplifier and I/O SI, and an output buffer OB. The memory cell array MA comprises a plurality of memory cells arranged in rows and columns for storing information. The address buffer AB receives external address signals to generate internal address signals. The X decoder ADX decodes an internal address signal applied from the address buffer AB to select a corresponding row in the memory cell array. The Y decoder decodes an internal column address signal applied from the address buffer AB to select a corresponding column in the memory cell array MA.
The sense amplifier and I/O SI detects and amplifies information stored in the selected memory cell in the memory cell array MA and outputs the information as read data to the output buffer OB in response to a signal from the Y decoder ADY. The output buffer OB receives the read data to output data OUT to the outside. A control signal generating system CG is provided as a peripheral circuit for generating signals for controlling timings of various operations in the DRAM.
FIG. 2 shows a schematic structure of the memory cell array portion of FIG. 1.
Referring to FIG. 2, the memory cell array MA comprises a plurality of word lines WL1, WL2, . . . , WLn and a plurality of bit lines BL0, BL0, BL1, BL1, . . . , BLM, BLm. Each of the word lines WL1, . . . , WLn is connected to one row of the memory cells. The bit lines form folded bit lines, in which two bit lines constitute a bit line pair. Namely, the bit lines BL0 and BL0 constitute a bit line pair, bit lines BL1 and BL1 constitute a bit line pair and the bit lines BLm and BLm constitute a bit line pair, in the same manner.
Memory cells 1 are connected to intersections of the bit lines BL0, BL0, . . . BLn, BLn and every other word lines. Namely, a memory cell is connected to an intersection of one word line and either one of the pair of bit lines. A precharging/equalizing circuit 150 for equalizing the potential of each bit line pair and precharging the same to a prescribed potential V.sub.B is provided at each bit line pair. A sense amplifier 50 is provided for each bit line pair, which is activated in response to signals .phi.A and .phi.B transmitted on signal lines 30 and 40 for detecting and differentially amplifying the potential difference between the bit line pair. Each of the bit lines is selectively connected to data input/output busses I/O, I/O in response to an address decode signal from the Y decoder ADY. Namely, the bit lines BL0 and BL0 are respectively connected to the data input/output busses I/O and I/O transfer gates T0 and T0'.
In a similar manner, the bit lines BL1, BL1 are connected to the data input/output busses I/O and I/O through transfer gates T1 and T1', and bit lines BLm and BLm are respectively connected to the data input/output busses I/O and I/O transfer gates Tm and Tm'. The address decoder signal from the Y decoder ADY is transmitted to the gates of the respective transfer gates T0, T0', . . . , Tm, Tm'. Thus a pair of bit lines is connected to the data input/output busses I/O and I/O.
FIG. 3 shows a detailed structure of one of the bit line pairs shown in FIG. 2. In FIG. 3, only one word line and one bit line pair are shown for the simplicity.
Referring to FIG. 3, a precharging/equalizing circuit 150 is provided for precharging a pair of bit lines 2 and 7 to a prescribed potential V.sub.B at the standby state of the memory and for equalizing the potential of the bit lines 2 and 7 at a prescribed potential. The precharging/equalizing circuit 150 comprises n channel MOS transistors 10 and 11 responsive to a precharging signal .phi..sub.P for electrically connecting these bit lines 2 and 7 by transmitting a prescribed precharge potential to the bit lines 2 and 7, and for equalizing the potential of the bit lines 2 and 7. Both of the n channel MOS transistors 10 and 11 become conductive in response to the precharging signal .phi..sub.P applied through the signal line 12 and apply the precharge potential V.sub.B on the signal line 9 to the bit lines 2 and 7.
The memory cell 1 is constituted by a transfer gate 5 formed of an n channel insulated gate field effect transistor and a capacitance 6. The transfer gate 5 has its gate connected to the word line 3 and its source connected to the bit line 2. The capacitance 6 is connected to the drain of the transfer gate 5 through a node 4, and the data of the memory cell 1 is stored in the node 4. The node 4 forms a so-called storage node.
When the word line 3 is selected, a word line driving signal Rn is sent to the transfer gate 5 to render the transfer gate 5 conductive, whereby the information stored in the memory cell 1 is transferred onto the bit line 2. A memory cell is connected to the bit line 2, while no memory cell is connected to the intersection between the word line 3 and the bit line 7. Therefore, when the memory cell 1 shown in FIG. 3 is selected, the bit line 7 applies the reference potential in association with the bit line 2 to the sense amplifier 50. The bit lines 2 and 7 respectively comprise parasitic capacitances 13 and 14.
Resistances 17 and 18 forming a constant voltage generating circuit are connected in series between the power supply 16 and the ground. A constant voltage defined by resistance division is generated at the node of the resistances 17 and 18. The resistance value of the resistances 17 and 18 are selected such that the level of the voltage is 1/2 of the common supply voltage. The output voltage of the constant voltage generating circuit is applied to the other electrode of the capacitance 6 through a signal line 8. The capacitance 6 is formed of a balanced plate electrode with the dielectric being a thin insulating film such as a single layer silicon oxide or a laminated film of silicon oxide and silicon nitride. The magnitude thereof is dependent on the area of the memory cell.
The area of the memory cell has been smaller and the memory cell capacitance has also been smaller as the degree of integration (memory capacitance) has been increased. In order to prevent malfunctions (soft errors) of a DRAM derived from .alpha. rays emitted from the outer package of the DRAM, the memory cell capacitance value of about 50 PF is required in general. Therefore, the reduction of the memory cell capacitance derived from the reduction of memory cell area has been compensated for by thinning the film thickness of the dielectric. However, when the film thickness of the dielectric is made thin, the electric field applied on the insulating film becomes strong, causing possible destruction of the insulating film and lowering the reliability of the DRAM. This disadvantage has become significant from 1M bit DRAMs which are actually used at present. In order to cope with the problem, a voltage half as large as the supply voltage provided by the division of the resistances 17 and 18 is supplied to the electrode (hereinafter referred to as a cell plate electrode) on the power supply side of the memory cell capacitance, as shown in FIG. 3. This method is disclosed in Japanese Patent Publication Gazette No. 50065/1985 (U.S. Ser. No. 722,841). According to this method, the electric field is determined by the voltage difference between the storage node 4 and the cell plate electrode, and the electric field becomes 1/2, since the voltage on the cell plate becomes the intermediate value between the data "1 " and "0".
However, the application of the voltage half as large as the supply voltage to the cell plate electrode makes it difficult to detect memory cells having small operation margins by V bump test. The reasons will be described in the following.
In the DRAMs of the capacitances less than 1M bit, the insulating film constituting the dielectric of the memory cell capacitance is relatively thick (about 150 .ANG..about.200 .ANG. in a DRAM of 256 k bit), and therefore, the voltage of the cell plate electrode need not be set at 1/2 Vcc. Therefore, a voltage of Vcc or 0 level is supplied from the power supply line or from the ground line which has small impedance and therefore little noise. The constant voltage generating circuit shown in FIG. 3 has relatively high impedance and noise is liable to occur during the operation of the DRAM to reduce operation margin thereof, so that it had not been used.
The effect of V bump test of cases in which the level of the cell plate electrode is power supply voltage Vcc, ground (fixed level) and Vcc/2 will be compared in the following.